Goals



PICPOT DESIGN GOALS:
TEACHING COMPLEX ELECTRONIC SYSTEM DESIGN





  • INTRODUCTION

    Satellites are not necessarily something huge and expensive. Small satellites have been designed (or are being designed) by several universities, as part of the engineering education process; they are mostly presented at SETC (Space Technology Education Conference, [1]). These satellites must fit within tight cost constraints, for the launch and the actual satellite hardware. They are usually launched using empty spaces available in the carriers of large commercial satellites (which makes launching costs affordable). Several such projects are under way and, to make possible design reuse and to keep costs as low as possible, some standards for the size and launch gear have been defined [2]. The educational benefits of small satellites for aerospace engineering education are already established [2]. This paper addresses the benefits for electronic engineering education, by describing the design and development of a small "educational" satellite named PicPot (acronym of the Italian words for Small Satellite of Politecnico di Torino). Emphasis is placed on the overall organization, design partitioning, some details of actual hardware, and the use of such projects in microelectronics education curricula.



  • THE EDUCATIONAL VALUES OF A SMALL SATELLITE

    It is clearly quite hard for small "university satellites" to achieve technical and scientific results comparable with "industrial" satellites, but they can be extremely useful from an educational point of view, for the following reasons:

    - Satellites and aerospace applications are attractors for good and motivated students: the project requires a consistent amount of work, and must comply hard time schedule (set by the launching date). Students who come to these projects are motivated, well prepared, and ready to work more than usual.

    - The interdisciplinarity and the complexity makes mandatory cooperation, both among different branches of engineers (structure, electronics, communication, ...), and within the "electronic" group itself (analog, digital, software, RF, ...). Completing such design is a good exercise of organization and team-working.

    - The overall system complexity brings towards structured design approach, with ample use of CAD tools in any design, realization, and testing phase. Such approach is closer to real industry (best) practice than the usual small project carried out within university curricula.

    As they are involved in the satellite project, students become exposed to the complete engineering flow: specification, design, development, assembly, and test. The process starts with specific constraints: size, weight from the satellite family specs, resources, payload, reliability, etc.); these must be translated into an architecture (set of modules and their interfaces). As the functions and the interface of each module are specified, the actual "electronic design" can start: After design, the modules must be built and tested. These steps require selection of components (from complex ICs to single R and C devices), design and fabrication of PCBs, assembly, definition of test procedures, preparation of test jigs and appropriate instrumentation setup. The complete set of issues to be addressed are not within grasp of a single designer - even less for a student. Therefore, to exploit the satellite design from ad educational point of view, it must be organized in specific tasks, each of which must be understandable and feasible by a single student (or a small group). Since each module is designed/built/tested by different people, a "design methodology" becomes mandatory to keep the process under control. All these issues converge to make the satellite design, development and test a very effective education environment, and a learning/training experience quite close to real-world practice for well-managed design processes.



  • SATELLITE ENVIRONMENTAL CONSTRAINTS

    Environmental constraints which are applied to the airborne satellite have been one of the leading issues during the design:

    1. temperature range; there is no clear indication of the temperature range of the satellite, both inside and outside the satellite mechanical structure. Indications from a satelllite design teamfrom anotther italian university indicated a range [-50, +150]°C outside the satellite. Thermal simulation of the PICPOT satellite, from thermal engineers of Politecnico indicated a range [0, +70]°C outside the satellite and a range [+30, +70]°C inside the satellite. This may cause some problem to batteries, while all the other components should not have problems.

    2. vacuum; this should cause no problem to electronical components, except for a reduced power dissipation (due to missing convection) of devices. Thermal simulations pointed out the most critical points, which might require additional ad-hoc dissipation.

    3. radiations

    4. vibrations during launch

    5. EMC



  • PICPOT Internal Architecture

    The PICPOT satellite is composed of a number of strictly interacting subsystems:

    1. Power conversion, which receives power from five GaAs solar panels, about 10x10cm2, nominal voltage 4.5V, peak power 1.3W, which are mounted around the satellite body. The power conversion system is made of as many hysterethic switchin power supplies. We have chosen that type of supply to reduce complexity, also considering that we could not use COTS supply, as they all were based on CMOS technology, therefore sensitive to latchups. Redundancy in the power conversion module is five-fold (one converter per each solar panel).

    Pannello Solare Mini


    2. Energy storage: electrical power from all converters can then be directed to either of six battery packs. Four of them are couples of Li-P batteries, delivering 7.2V nominal and 1500mAh per pack. The other two packs are composed of 6 AA NiCd elements, delivering 7.2V nominal and 900mAh. We have chosen to have different types of batteries to have some design redundancy, as we did not have enough data on the behaviour of COTS batteries in space. Only on e battery can be charged at any given instant, for a max of 12 hours each. Charging strategy (based on battery voltage and temperature) is distributed between the two housekeeping processors (see further), which caindependenlty of each other, define which battery to charge. This avoids having computation capabilities on the power conversion board and allows a fault-tolerant, fail-operational-fail-safe approach to battery charging. The six battery packs are grouped in two groups of three batteries (2 Li-P and 1 NiCd), each supplying one of two hot-redundant housekeeping and telecommunication chains (A and B), via as many power busses.

    3. Energy management systems: a number of sensors are there to continusoulsy measure voltage, current and temperature of each solar panel and battery. Measurements are multiplexed and sampled every 30s, alteratively from each of the two houskeeping processors (see further). Multiplexers are partially redundant, for a fail-operational-fail-stop approach with some degradation at the first fault.

    4. Timing and power management systems: each power bus (A and B) supplies a timing and power management system, which periodically turns one of the two houskeeping and data management subsystems on, by properly providing supply to the corresponding housekeeping processor (3.3V and 5V) and the associated transceiver (3.3V and 5V). Each processor and transceiver is woken up every 60s, for not more than 55s, allowing at least 5s off each minute. This refrains from using the watchdog timers, which would monitor potential hangups due to single-event upsets, drastically simlifiying the software of the processors. The two chains (A and B) are woken up with 30s delays from each other. We have designed a fault-tolerant synchronization strategy between the two chains. The two power management systems are built with two different COTS processors (a Microchip PIC and a Texas Instruments MSP430), to have some design redundancy

    5. Housekeeping and data handling processors: as mentioned above, PICPOT contains two hot-redundant housekeeping chains (A and B). Each housekeeping processors has the duty to: i) periodically sample housekeeping data from the power conversion, energy storage and transceiver subsystems; ii) store housekeeping data for about 2 ours; iii) receive telecommands from grond station via the RF receiver; iv) handle telecommands and transfer all the relevant to the payload; v) assemble and transmit to ground via the RF transmitter all housekeeping data; iv) receive (when requested to to so) data (images) from the payload and transmit them to ground; vii) drive a torque motor based on a reaction wheel and a brushless motor (this is the only functionality og PICPOT which is not redundant and is associated with only the processor of chain B). The two housekeeping subsystems are built with two different COTS processors (a Chipconn CC1010 and a Texas Instruments MSP430), to have some design redundancy. Also different tpes of static, flash and ferroelectric RAM devices have been used.

    6. RF transceivers: two half duplex transceivers, one per each housekeeping chain. Chain A operates at around 437MHz, uses the APRS (a variation of AX25) radio-amateur protocol at 9,600 bits/s with FSK modulation, 6kHz frequency deviation. The transceiver feeds a double helical antenna which is mounted on the only face of PICPOT which has no solar panel. Transmitted power is 33dBm, while receiver sensitivity is -105dBm. Chain B operates at around 2.4GHz, uses a protocol similat to the APRS radio-amateur protocol but at 10,000 bits/s with FSK modulation, 100kHz frequency deviation. Transmitted power is 30dBm, while receiver sensitivity is -100dBm. The transceiver feeds a patch antenna which is mounted on the only face of PICPOT which has no solar panel. We have chosen to have two completely different frequencies (although both in the radio-amateur bands), both to have design redundancy and to take advantage of the complementary radiation patterns of the two antennas (one mostly along the satellite spin axis, while the other mostly on the plane perpendicular to it). This should guarantee a reliable communication on at least one of the two chains independently of the satellite attitude (which cannot be controlled reliably). Power budget is such as to guarantee 10-10 bit error rate in the uplink (as the ground station has more than 40dBm power) and 10-6 bit error rate (10-4 worst case) in the downlink.

    7. Payload: wehave decided to carry, as payload, three color cameras. Cameras were manufactured with standard COTS modules, but assembed purposedly with a lens and sealed with vacuum inside by ITEM s.r.l. The three cameras have different focal lengths for different resolutions (pixel size on ground of about 100m, 200m, 400m, respectively). Images are output as PAL signals from the camera modules, decoded and acquired with COTS devices (a Texas Instrument video decoder and an Analog Devices BlackFinn processor). The processor also compresses (JPEG; 30s max conversion time) and stores up to 5 images into the on-boad flash. Images are then transferred (upon request from ground) to either of the housekeeping processors and then transferred to ground via the corresponding downlink. The payload is not redundant.

    8. Ground station: we have used commercial radio systems and TNC at 437MHz, while we have developped an ad-hoc transceiver with commercial power amplifiers. As regards antennas, we have used an ad-hoc helical antenna at 437MHz plus a commercial 1.3m parabola at 2.4GHz. Both antennas are mounted on a single commercial rotor interfaced to a PC and a connection to the NORAD system to predict satellite position.



  • Satellite Boards

    All the subsystems mentioned above use standard and cheap COTS (Commercial Off The Shelf) electronic components. We have used no preassembled module, except for the three PAL cameras. All devices have been mounted on six 1.5mm PCB's manufactured with standard and cheap technology for earth applications. Each board has been designed and manufactured in two steps: i) design, manufacture and test of a prototype board, not compliant with mechanical constraints, but bearing a number of additional test points and features; only one exemplar of each prototype board has been populated with components by the students of the design team; ii) tuning, manufacture and test of the final board, compliant with all constraints, ready for launch; three exemplars of each final board have been populated and manufactured by a skilled professor, to guarantee a higher quality level. Development and tuning obviously includes also all relevant software. We have completely designed from scratch the following boards:

    1. Power Supply, hosting the five power converters and all houskeeping signal conditioners for solar panels and batteries. This board has been designed by a team made of two students (full-time, 6 months each), a PhD and two professors (both part-time); it has been tuned, assembled and tested by a research fellow (full-time, 1 month) and a professor (part-time) with a total effort of 1.5 manyear;

    PowerSupply Mini


    2. Power Switch, hosting the timing and power management subsystems for both chains. This board has been designed by a team made of four students (full-time, 6 months; two for each of the two chains, A and B; two for the HW and two for the SW) and a professor (part-time); it has been tuned, assembled and tested by another team made of two students (full-time, 6 months) and two professors (part-time) with a total effort of 2.5 manyears;

    PowerSwitch Mini


    3. Processor A and Processor B: two similar boards hosting the housekeeping and data handling processor and some signal conditioning for chains A and B, respectively. Each board has been designed by a team made of two students (full-time, 6 months; one for the HW and one for the SW) and a professor (part-time); it has been tuned, assembled and tested by the same team, with an average total effort of 2 manyear per ach board;

    ProcA Mini          ProcB Mini


    4. TxRx, hosting the RF transceivers of both chains. This board has been designed by a team made of two student (full-time, 6 months each) and a professor (part-time); it has been tuned, assembled and tested by a professor (full-time, 1 month) but without students with a total effort of 1.5 manyear;

    TxRx Mini


    5. Payload, hosting the payload processor and interfaced to the three cameras, which are assembled onto the satellite external structure. This board has been designed by a team made of two students (full-time, 6 months each; one for the HW and one for the SW) and a professor (part-time); it has been tuned, assembled and tested by another team made of one student (full-time, 6 months) and a professor (part-time), with a total effort of 1.5 manyear;

    Payload Mini


    6. Both airbone antennas are assembled on the external structure of the satellite, while ground antennas are mounted on the roof of Politecnico. Antennas has been designed, assembled and tested by a team made of a PhD student (full-time, 2 months) and a professor (part-time), with a total effort of 0.5 manyears;

    Antenne Picpot Mini


    7. Ground station has been developped by assembling commercial radio-amateur systems plus manufacuting some ad-hoc boards and antennas. Total effort has been about 1.5 manyear;

    Antenne Mini


    8. Satellite mechanical structure has been designed by a team from the Aereospace Engineering Department, together with the Physics Department of our Politecnico.

    The total effort for the design, tuning, manufacturing, testing of the whole satellite has therefore been of about 10 student manyears plus about 1.5 professor and PhD manyears, and about 1 manyear of coordination effort.



  • CONCLUSIONS

    Having a small satellite designed and developed by students has a high educational value, since they have to go through all steps, including selection of components, final implementation and testing. The main challenges for educators are to define a workflow (specification, design, fabrication, testing) and to structure the design process in parts affordable by students. A new satellite design is under way. While we try to reuse most of the design at the "module" level, we are evaluating different choices to achieve redundancy. Another issue at the architectural level is the modularity. We plan to follow more strictly a top-down approach, also to make possible the insertion of different payloads within the same basic satellite structure.



  • REFERENCES

    [1] Space Technology Education Conference, http://space.epfl.ch/page40841.html and http://www.stec2005.space.aau.dk/index.php

    [2] Alminde L., Educational Benefits from the AAU-cubesat Student Satellite Project, AAIA/IAC, 2003. IAC 2003 conference paper : IAC 03-01-P.1-08

    [3] Twiggs B., Puig-Suari J., CUBESAT Design Specification Document, Stanford University and Polytechnical