Fourth Workshop on

Interconnection Network Architectures:
On-Chip, Multi-Chip
(INA-OCMC 2010)

Held in conjunction with the:
5th International Conference on High Performance Embedded Architectures and Compilers (HiPEAC)
Pisa, Italy, January 24, 2010

Program available
(click here)

Keynote speaker
Luca Benini
from University of Bologna
(click here)

Embedded and other computation systems no longer operate in isolation, but are interconnected in various ways. While bus-based or wireless communication can be used in low-throughput applications, mainstream trends for high-performance designs turn to switch-based interconnections using point-to-point links.

This workshop concerns interconnection network architectures, whether on-chip or multi-chip.

Topics of interest

Topics of interest, within the context of interconnection networks, include but are not limited to:

Networks-on-Chip (NoC)
Multi-Chip Interconnection Networks, including Cluster Inteconnects
"Commodity Switches" as general-purpose building blocks
Switching, buffering, and routing architectures
Flow control and congestion management in switching fabrics
Virtualization
Reliability, availability, fault tolerance
Synchronization issues
Area/power versus functionality/QoS support in NoC architectures
Design space exploration
Mapping techniques and methodologies
NoC programming models and benchmarking
NoC testing and verification

The goal of the workshop is to provide a forum for presenting and discussing mostly work in progress, or ideas for future research in response to future trends.
Submissions from EU projects in progress as well as seminal work and new ideas to stimulate advances in the field are specifically encouraged.
Work-in-progress papers with few experimental results are welcome, as long as they have been carefully thought out and are intuitively sound and implementable.

This is the fourth year of the workshop. In the previous editions the workshop exhibited a competent audience and interesting discussions arose from the different presentations of authors and from the keynote.

Important dates

Hard Submission Deadline: November 30th, 2009 (FIRM)
Notification to authors: December 18th, 2009
Workshop: January 24th, 2010 (half day)

Paper submission

Both research and application-oriented papers are welcome.
The submission procedure will be through the EasyChair web-page (direct link here).

Papers must be in PDF format and should include title, authors and affiliation, e-mail address of the contact author.

Submissions must be limited to 4 pages (two columns, 10pt).
Papers deviating significantly from these paper size and formatting rules may be rejected without review.

Organizers

General Chairs:
- José Flich - Technical University of Valencia (Spain)
- Davide Bertozzi - University of Ferrara (Italy)
Program Chairs:
- Tor Skeie - Simula Research Labs (Norway)
- Marcello Lajolo - NEC Laboratories America (USA)
Publicity Chair:
- Daniele Ludovici - TU Delft (The Netherlands)
Steering Committee:
- José Duato - Technical University of Valencia (Spain)
- Manolis Katevenis - FORTH-ICS (Greece)

Program committee

Olav Lysne, Simula Research Labs (Norway)
Ulrich Brüning, Univ. Heidelberg (Germany)
Marcello Coppola, STMicroelectronics (France)
Ran Ginosar, Technion (Israel)
Janusz Kleban, Poznan Univ. of Technology (Poland)
Cyriel Minkenberg, IBM (Zurich)
Robert Mullins, Univ. Cambridge (UK)
José Luis Sánchez, UCLM (Spain)
Li Shiuan Peh - MIT (USA)
Pascal Vivet - CEA-LETI (France)
Pedro Javier García - University of Castilla-La Mancha (Spain)
Sudhakar Yalamanchili - Georgia Institute of Technology (USA)
Partha Kundu - INTEL (USA)
Maurizio Palesi - University of Catania (Italy)
Giorgos Dimitrakopoulos - Univ. of West Macedonia, Kozani (Greece)
José Angel Gregorio - Univ. of Cantabria (Spain)
Dionisios Pnevmatikatos - ICS-FORTH (Greece)
Kees Goessens - NXP and TU Delft (The Netherlands)
Dimitris Lioupis - University of Patras (Greece)

Program

TIME	EVENT
08:30 - 08:40	Welcome Address
08:40 - 09:40	Keynote: NoC design for Next-Generation Computing Platforms Luca Benini - University of Bologna, Italy
09:40 - 10:05	Simple and Efficient Implementation of NoC switches with Statically Allocated Virtual Channels for Multi-Processor Systems-on-Chip Davide Bertozzi, Simone Medardoni, Francisco Gilabert and Maria Engracia Gomez - University of Ferrara, Italy and Universidad Politecnica de Valencia, Spain
10:05 - 10:30	An Adaptive Routing Technique Supporting In-Order Packet Delivery in Networks on Chip Maurizio Palesi, Rickard Holsmark, Xiaohang Wang, Shashi Kumar, Mei Yang, Yingtao Jiang and Vincenzo Catania - University of Catania, Italy and Jönköping University, Sweden and University of Nevada, Las Vegas, USA
10:30 - 11:00	Coffee break
11:00 - 11:25	A Novel Hardware-based Barrier Synchronization for Many-Core CMPs José L. Abellán, Juan Fernández and Manuel E. Acacio - Universidad de Murcia, Spain
11:25 - 11:50	Effect of the CMP Network on the PARSEC v2.1 Benchmark Suite Scalability Francisco Triviño-García, José Luis Sánchez-García and Francisco José Alfaro-Cortés - University of Castilla-La Mancha, Spain
11:50 - 12:15	HTAX: A Novel Framework for Flexible and High Performance Networks-On-chip Heiner Litz, Holger Froening and Ulrich Bruening - University of Heidelberg, Germany
12:15 - 12:40	Impact of Interconnection Network Resources on CMP Performance Pablo Abad, Pablo Prieto, Javier Merino, Lucia Gregorio and Valentin Puente - University of Cantabria, Spain
12:40 - 12:50	Closing followed by lunch

Keynote

Keynote speaker:

Luca Benini, University of Bologna (Italy)

Keynote title:

NoC design for Next-Generation Computing Platforms

Abstract:

Networks on Chip are the backbone of current and future SoC scalable computing platforms. As silicon technology moves aggressively into the nanometer region, and NoCs mature from research vision to mature technology, the bar is set higher: NoC solutions should provide a complete answer to new technology and architectural challenges, many of which lie at the boundary of the communication fabric. In this talk I will focus on synchronization, heterogeneous memory interfaces and vertical stacking. These three NoC design challenges, and possible solutions will be described in the context of STMicroelectronics' Platform2012 next-generation embedded computing platform.

Luca Benini's Short bio:

Luca Benini is a Full Professor at the University of Bologna. He also holds a visiting faculty position at the Ecole Polytecnique Federale de Lausanne (EPFL). He received a Ph.D. degree in electrical engineering from Stanford University in 1997. Dr. Benini's research interests are in the design of systems for ambient intelligence, from multi-processor systems-on-chip/networks on chip to energy-efficient smart sensors and sensor networks.From there his research interest have spread into the field of biochips for the recognition of biological molecules, and into bioinformatics for the elaboration of the resulting information and further into more advanced algorithms for in silico biology. He has published more than 300 papers in peer-reviewed international journals and conferences, three books, several book chapters and two patents. He has been program chair and vice-chair of Design Automation and Test in Europe Conference. He has been a Member of the 2003 MEDEA+ EDA roadmap committee 2003. He is a member of the IST Embedded System Technology Platform Initiative (ARTEMIS): working group on Design Methodologies, a Member of the Strategic Management Board of the ARTIST2 Network of excellence on Embedded Systems and a Member of the Advisory group on Computing Systems of the IST Embedded Systems Unit. He has been member of the technical program committee and organizing committee of several technical conferences, including the Design Automation Conference, International Symposium on Low Power Design, the Symposium on Hardware-Software Codesign. He is Associate Editor of the IEEE Transactions on Computer-Aided Design of Circuits and Systems and of the ACM Journal on Emerging Technologies in Computing Systems. He is a Fellow of the IEEE.