01GQSHT 01GQSCY - Microelectronics

Prof. Luciano Lavagno

Computer engineering Master's degree (Corso di Laurea Specialistica in Ingegneria Informatica)

Politecnico di Torino

Here is the old version of the course program, in Italian. It is still valid for students from before 2007 (and essentially the same as the current program).

Course objectives

This course provides the students with an in-depth look at the circuit and layout design techniques for CMOS standard cells, as well as an overview of modern Electronic Design Automation tools and flows. It starts by reviewing the behavior of MOS transistors and interconnect structures. Then it illustrates how transistors are combined to create logic gates for the main logic families, considering the corresponding area, delay, power and robustness trade-offs. Combinational and sequential gates, using both static and dynamic logic are discussed. Clocking strategies for sequential logic are described, as well as performance optimization strategies by transistor sizing. Finally it provides an overview of the complete RTL-to-GDSII flow that is used today for implementation of digital circuits.

Course prerequisites

The course assumes previous knowledge of:

• Distinction between digital and analogue circuits, active and passive components, linear and non-linear models, noise margins.
• Modeling and analysis of resistor/capacitor linear networks with current and voltage sources.
• Modeling and analysis of PMOS and NMOS transistors.

Previous knowledge of logic design is useful, but not strictly required.

Course topics

• Evolution of microelectronics, Moore's law
• Review of MOS transistor behavior
• CMOS fabrication process, design rules
• Static combinational CMOS logic
  • CMOS Inverter
  • Transistor sizing, threshold voltage, propagation and transition delays
  • Power consumption
  • Complex logic gates: NAND, NOR, AOI, OAI
  • Decoders and multiplexers
  • Delay optimization by transistor sizing, logical effort
• Other CMOS combinational logic families
  • Pass transistors and transmission gates
  • Dynamic domino logic
• Static and dynamic sequential CMOS logic
  • Set-reset and transparent latches
  • Metastability, setup and hold times
  • Flip-flops
  • Clocking strategies and clock distribution
• CMOS memories: ROMs, static and dynamic RAMs
• Interconnect: lumped RC model, Elmore model
• ASIC design flow
  • HDL specification and simulation
  • Logic synthesis and static timing analysis
  • Placement and routing
• Fault models, scan design, test pattern generation

Suggested books

Attending classes and taking notes is generally sufficient (no extra material is required). Course notes taken by students in 2006-2007 and roughly revised by the instructor are available. An Italian version is in also available.

Who prefers to use a textbook can purchase: Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolicī, ``Digital Integrated Circuits'', Prentice-Hall, 2003, (available also in Italian).

Here are the slides from Rabaey's text (plus some in Italian by prof. Gregoretti) in powerpoint, postscript or PDF.

The second part of the course, on the ASIC design flow, is not covered well by any text book. Here are the slides from Kurt Keutzer's course in Berkeley, which go beyond what is covered in the course.

Laboratory

Four or five 4-hour lab sessions cover the design and simulation of CMOS transistors, of an inverter, and a simple design flow example. Here is the lab guide in Italian (the English version is also in preparation).

Course projects

Groups of 1-3 people can work on a project, which replaces part of the exam, and provides an opportunity for more in-depth work with our research group. Please, discuss with the instructor if interested.

Final exam

The final exam is typically oral and consists of two or three questions. The first question can be the project discussion (for people who have chosen it), or it can be asked in written form immediately before the oral exam (30 minutes; text books and notes can be used). Some sample questions from past years are available.

Office hours

The instructor is generally available during the term. Availability during the summer is sporadic.

• Please look at the travel plans section in the instructor's WEB page: http://polimage.polito.it/~lavagno
• E-mail: luciano.lavagno@polito.it
• Office phone: 011 5644150
• Cell phone (used as a work phone; feel free to call): 348 6003714