Luciano Lavagno's publications

1

A. Bonomo, M. Italiano, L. Lavagno, M. L. Maggiulli, M. Melgara, M. Paolini, and I. Stamelos.
BACH (Behavioural-level Automated Compilation of Hardware): an integrated ASIC synthesis system.
In ESPRIT Technical Week, 1988.

2

L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli.
Synthesis of verifiably hazard-free asynchronous control circuits.
Technical Report UCB/ERL M90/99, U.C. Berkeley, 1990.

3

L. Lavagno, S. Malik, R.K. Brayton, and A. Sangiovanni-Vincentelli.
MIS-MV: Optimization of multi-level logic with multiple-valued inputs.
In Proceedings of the Int'l Conference on Computer-Aided Design, pages 560-563, November 1990.

4

L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli.
Synthesis of verifiably hazard-free asynchronous control circuits.
In Proceedings of the Conference on Advanced Research in VLSI, March 1991.

5

L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli.
Algorithms for synthesis of hazard-free asynchronous circuits.
In Proceedings of the Design Automation Conference, June 1991.

6

L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli.
Synthesis for testability techniques for asynchronous circuits.
In Proceedings of the International Conference on Computer-Aided Design, November 1991.

7

L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli.
Synthesis for testability techniques for asynchronous circuits.
Technical Report UCB/ERL M91/67, U.C. Berkeley, 1991.

8

L. Lavagno.
Synthesis and Testing of Bounded Wire Delay Asynchronous Circuits from Signal Transition Graphs.
PhD thesis, U.C. Berkeley, November 1992.
Technical report UCB/ERL M92/140.

9

L. Lavagno, S. Malik, R.K. Brayton, and A. Sangiovanni-Vincentelli.
Symbolic minimization of multilevel logic and the input encoding problem.
IEEE Transactions on Computer-Aided Design, 11(7):825-843, July 1992.

10

L. Lavagno, C. W. Moon, R. K. Brayton, and A. Sangiovanni-Vincentelli.
Solving the state assignment problem for signal transition graphs.
In Proceedings of the Design Automation Conference, June 1992.

11

L. Lavagno, C. W. Moon, R. K. Brayton, and A. Sangiovanni-Vincentelli.
A novel framework for solving the state assignment problem for event-based specifications.
Technical Report UCB/ERL M92/19, U.C. Berkeley, 1992.

12

L. Lavagno and A. Sangiovanni-Vincentelli.
Linear programming for optimal hazard removal in asynchronous circuits.
In Proceedings of the International Conference on Computer Design, October 1992.

13

E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli.
SIS: A system for sequential circuit synthesis.
Technical Report UCB/ERL M92/41, U.C. Berkeley, May 1992.

14

A. V. Yakovlev, L. Lavagno, and A. Sangiovanni-Vincentelli.
A unified signal transition graph model for asynchronous control circuit synthesis.
In Proceedings of the International Conference on Computer-Aided Design, November 1992.

15

A. V. Yakovlev, L. Lavagno, and A. Sangiovanni-Vincentelli.
A unified signal transition graph model for asynchronous control circuit synthesis.
Technical Report UCB/ERL M92/78, U.C. Berkeley, July 1992.

16

M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, and A. Sangiovanni-Vincentelli.
A formal specification model for hardware/software codesign.
Technical Report UCB/ERL M93/48, U.C. Berkeley, June 1993.

17

M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, and A. Sangiovanni-Vincentelli.
Synthesis of mixed software-hardware implementations from CFSM specifications.
Technical Report UCB/ERL M93/49, U.C. Berkeley, June 1993.

18

M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, and A. Sangiovanni-Vincentelli.
A formal specification model for hardware/software codesign.
In Proceedings of the International Workshop on Hardware-Software Codesign, 1993.

19

M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, and A. Sangiovanni-Vincentelli.
Synthesis of mixed software-hardware implementations from CFSM specifications.
In Proceedings of the International Workshop on Hardware-Software Codesign, 1993.

20

L. Lavagno.
Sintesi di Circuiti VLSI Asincroni.
PhD thesis, Politecnico di Torino, Italy, March 1993.

21

L. Lavagno, M. Kishinevsky, and A.Lioy.
Testing redundant asynchronous circuits.
Technical Report ID-TR: 1993-124, Technical University of Denmark, October 1993.

22

L. Lavagno and A. Sangiovanni-Vincentelli.
Synthesis of asynchronous circuits with bounded delays: an example.
In proceedings of the Working Conference on Asynchronous Design Methodologies, March 1993.

23

L. Lavagno and A. Sangiovanni-Vincentelli.
Automated synthesis of asynchronous interface circuits.
Microprocessors and Microsystems, May 1993.

24

L. Lavagno and A. Sangiovanni-Vincentelli.
Algorithms for synthesis and testing of asynchronous circuits.
Kluwer Academic Publishers, 1993.

25

A. V. Yakovlev, A. I Petrov, and L. Lavagno.
A high speed asynchronous arbiter.
Technical Report TR No.427, Computing Science, University of Newcastle upon Tyne, May 1993.

26

A.V. Yakovlev, M. Kishinevsky, A.Y. Kondratyev, and L. Lavagno.
On the models for asynchronous circuit behaviour with OR causality.
Technical Report TR 463, University of Newcastle upon Tyne Computing Laboratory, December 1993.

27

A.V. Yakovlev, A.M. Koelmans, and L. Lavagno.
High level modelling and design of asynchronous interface logic.
Technical Report TR 460, University of Newcastle upon Tyne Computing Laboratory, November 1993.

28

A. Broggi, G. Conte, L. Lavagno, F. Gregoretti, C. Sansoè, and L. Reyneri.
PAPRICA-3: a real-time morphological image processor.
In Proceedings of 1st International Conference on Image Processing, November 1994.

29

M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, and A. Sangiovanni-Vincentelli.
Synthesis of software programs from CFSM specifications.
Technical Report UCB/ERL M94/87, U.C. Berkeley, 1994.

30

M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, and A. Sangiovanni-Vincentelli.
Hardware/software codesign of embedded systems.
IEEE Micro, 14(4):26-36, August 1994.

31

J. Cortadella, L. Lavagno, P. Vanbekbergen, and A. Yakovlev.
Designing asynchronous circuits from behavioural specifications with internal conflicts.
Technical Report RR 94/08 UPC/DAC, Universitat Politecnica de Catalunya, May 1994.

32

J. Cortadella, L. Lavagno, P. Vanbekbergen, and A. Yakovlev.
Designing asynchronous circuits from behavioural specifications with internal conflicts.
In International Symposium on Advanced Research in Asynchronous Circuits and Systems, Salt Lake City, Utah, November 1994.

33

L. Lavagno, M. Chiodo, P. Giusto, H. Hsieh, S. Yee, K. Suzuki, A. Jurecska, and A. Sangiovanni-Vincentelli.
A case study in computer-aided codesign of embedded controllers.
In Proceedings of the International Workshop on Hardware-Software Codesign, 1994.

34

L. Lavagno, M. Kishinevsky, and A.Lioy.
Testing redundant asynchronous circuits.
In proceedings of the European Design Automation Conference (Euro-DAC), September 1994.

35

L. Lavagno, N. Shenoy, and A. Sangiovanni-Vincentelli.
Linear programming for hazard elimination in asynchronous circuits.
Journal of VLSI Signal processing, 7(1-2):137-160, 1994.

36

A. V. Yakovlev, A. I Petrov, and L. Lavagno.
A low latency asynchronous arbitration circuit.
IEEE Transactions on VLSI Systems, pages 372-377, September 1994.

37

A.V. Yakovlev, M. Kishinevsky, A.Y. Kondratyev, and L. Lavagno.
OR causality: Modelling and hardware implementation.
In International Conference on Application and Theory of Petri Nets, Zaragoza, Spain. IEEE Computer Society, June 1994.

38

M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, and A. Sangiovanni-Vincentelli.
Synthesis of software programs from CFSM specifications.
In Proceedings of the Design Automation Conference, June 1995.

39

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev.
A region-based theory for state assignment in asynchronous circuits.
Technical Report 95-2-006, University of Aizu, Japan, October 1995.

40

J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev.
Synthesizing Petri nets from state-based models.
Technical Report RR 95/09 UPC/DAC, Universitat Politecnica de Catalunya, April 1995.

41

J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev.
Synthesizing Petri nets from state-based models.
In Proceedings of the International Conference on Computer-Aided Design, November 1995.

42

K. Keutzer, L. Lavagno, and A. Sangiovanni-Vincentelli.
Synthesis for testability techniques for asynchronous circuits.
IEEE Transactions on Computer-Aided Design, 14(12):1569-1577, December 1995.

43

L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli.
Synthesis of hazard-free asynchronous circuits with bounded wire delays.
IEEE Transactions on Computer-Aided Design, January 1995.

44

L. Lavagno, P. McGeer, A. Saldanha, and A. Sangiovanni-Vincentelli.
Timed Shannon circuits: a power-efficient design style and synthesis tool.
In Proceedings of the Design Automation Conference, June 1995.

45

L. Lavagno, C. W. Moon, R. K. Brayton, and A. Sangiovanni-Vincentelli.
An efficient heuristic procedure for solving the state assignment problem for event-based specifications.
IEEE Transactions on Computer-Aided Design, January 1995.

46

A. V. Yakovlev, A. M. Koelmans, and L. Lavagno.
High level modelling and design of asynchronous interface logic.
IEEE Design and Test, Spring 1995.

47

A. Agrawal, A. Saldanha, L. Lavagno, and A. Sangiovanni-Vincentelli.
Compact and complete test set generation for multiple stuck-at faults.
In Proceedings of the International Conference on Computer-Aided Design, November 1996.

48

F. Balarin, H. Hsieh, A. Jurecska, L. Lavagno, and A. Sangiovanni-Vincentelli.
Formal verification of embedded systems based on CFSM networks.
In Proceedings of the Design Automation Conference, 1996.

49

G. Cabodi, P. Camurati, L. Lavagno, E. Macii, M. Poncino, S. Quer, and E. Sentovich.
Enhancing fsm traversal by temporary re-encoding: .
In Proceedings of the International Conference on Computer Design, October 1996.

50

S. Cardelli, M. Chiodo, P. Giusto, A. Jurecska, L. Lavagno, and A. Sangiovanni-Vincentelli.
Rapid-prototyping of embedded systems via reprogrammable devices.
In 7th IEEE International Workshop on Rapid System Prototyping, 1996.

51

M. Chiodo, D. Engels, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, K. Suzuki, and A. Sangiovanni-Vincentelli.
A case study in computer-aided codesign of embedded controllers.
Design Automation for Embedded Systems, 1(1-2), January 1996.

52

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev.
Complete state encoding based on the theory of regions.
In International Symposium on Advanced Research in Asynchronous Circuits and Systems, Aizu, Japan, March 1996.

53

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev.
Methodology and tools for state encoding in asynchronous circuit synthesis.
In Proc. of the 33rd. Design Automation Conference, June 1996.

54

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev.
Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers.
In Proc. of the 11th Conf. Design of Integrated Circuits and Systems, Barcelona, Spain, November 1996.

55

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev.
Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers.
IEICE Transactions on Information and Systems, 1996.

56

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev.
Coupling technology mapping, logic optimization and state encoding.
Technical report, Universitat Politecnica de Catalunya, April 1996.

57

J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev.
Deriving Petri nets from finite transition systems.
Technical Report UPC-DAC-1996-19, Dept. of Computer Architecture, Universitat Politècnica de Catalunya, June 1996.

58

J. Cortadella, M. Kishinevsky, L. Lavagno, A. Yakovlev, and A. Kondratyev.
Petrify: a tool for synthesis of Petri nets.
In 17th International Conference on Applications and Theory of Petri Nets, June 1996.

59

F. Gregoretti, F. Intini, L. Lavagno, R. Passerone, L. Reyneri, and C. Sansoè.
Design and implementation of the control structure of the PAPRICA-3 processor.
In Proceedings of the Fourth Euromicro Workshop on Parallel and Distributed Processing, January 1996.

60

M. Kishinevsky, J. Cortadella, A. Kondratyev, L. Lavagno, and A. Yakovlev.
Synthesis of General Petri Nets.
Technical Report 96-2-004, University of Aizu, Japan, November 1996.

61

M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Saldanha, and A. Taubin.
Hazard free robust path delay fault testing of asynchronous nets.
Technical Report TR: 96-2-001, The University of Aizu, Japan, March 1996.

62

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev.
Technology mapping for speed-independent circuits based on decomposition and resynthesis.
Technical Report TR: 96-10-002, The University of Aizu, Japan, October 1996.

63

L. Lavagno, A. Sangiovanni-Vincentelli, and H. Hsieh.
Models and algorithms for embedded system synthesis and validation.
In G. De Micheli, editor, Nato Advanced Study Institute. Kluwer Academic Publisher, 1996.

64

C. Passerone, M. Chiodo, W. Gosti, L. Lavagno, and A. Sangiovanni-Vincentelli.
Evaluation of trade-offs in the design of embedded systems via co-simulation.
Technical Report UCB/ERL M96/12, U.C. Berkeley, 1996.

65

S. Quer, G. Cabodi, P. Camurati, L. Lavagno, E. Sentovich, and R.K. Brayton.
Incremental re-encoding for symbolic traversal of product machines.
In Proceedings of the European Design Automation Conference, September 1996.

66

R. von Hanxleden, J. Bohne, L. Lavagno, and A. Sangiovanni-Vincentelli.
Hardware/Software Co-Design of a Fault-Tolerant Communication Protocol.
In Proceedings of the IEEE International Workshop on Embedded Fault-Tolerant Systems, Dallas, TX, September 1996.

67

A. V. Yakovlev, M. Kishinevsky, A.Y. Kondratyev, L. Lavagno, and M. Pietkiewicz-Koutny.
On the models for asynchronous circuit behaviour with OR causality.
Formal Methods in System Design, pages 189-234, November 1996.

68

A. V. Yakovlev, L. Lavagno, and A. Sangiovanni-Vincentelli.
A unified signal transition graph model for asynchronous control circuit synthesis.
Formal Methods in System Design, pages 139-188, November 1996.

69

F. Balarin, M. Chiodo, L. Lavagno, A. Jurecska, B. Tabbara, and A. Sangiovanni-Vincentelli.
Automatic generation of a real-time operating system for embedded systems.
In Proceedings of the International Workshop on Hardware-Software Codesign, March 1997.

70

F. Balarin, E. Sentovich, M. Chiodo, P. Giusto, H. Hsieh, B. Tabbara, A. Jurecska, L. Lavagno, C. Passerone, K. Suzuki, and A. Sangiovanni-Vincentelli.
Hardware-Software Co-design of Embedded Systems - The POLIS approach.
Kluwer Academic Publishers, 1997.

71

G. Cabodi, P. Camurati, L. Lavagno, and S. Quer.
Verification and synthesis of counters based on symbolic techniques.
In Proceedings of the European Design Automation and Testing Conference (EDTC), March 1997.

72

G. Cabodi, P. Camurati, L. Lavagno, and S. Quer.
Disjunctive partitioning and partial iterative squaring: An effective approach for symbolic traversal of large circuits.
In Proceedings of the Design Automation Conference, June 1997.

73

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev.
Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis.
In Proceedings of the European Design Automation and Testing Conference (EDTC), March 1997.

74

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev.
Decomposition and technology mapping of speed-independent circuits using boolean relations.
In Proceedings of the International Conference on Computer-Aided Design, November 1997.

75

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev.
A region-based theory for state assignment in asynchronous circuits.
IEEE Transactions on Computer-Aided Design, 16(8):793-812, August 1997.

76

J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev.
Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers.
IEICE Transactions on Information and Systems, E80-D(3):315-325, March 1997.

77

S. Edwards, L. Lavagno, E.A. Lee, and A. Sangiovanni-Vincentelli.
Design of embedded systems: formal models, validation, and synthesis.
Proceedings of the IEEE, 85(3):366-390, March 1997.

78

H. Hsieh, L. Lavagno, C. Passerone, C. Sansoè, and A. Sangiovanni-Vincentelli.
Modeling micro-controller peripherals for high-level co-simulation and synthesis.
In Proceedings of the International Workshop on Hardware-Software Codesign, March 1997.

79

M. Kishinevsky, J. Cortadella, A. Kondratyev, L. Lavagno, A. Taubin, and A. Yakovlev.
Coupling asynchrony and interrupts: Place Chart Nets and their synthesis.
In 18th International Conference on Application and Theory of Petri Nets, Toulouse, France, June 1997.

80

M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Saldanha, and A. Taubin.
Partial scan delay fault testing of asynchronous circuits.
In Proceedings of the International Conference on Computer-Aided Design, November 1997.

81

M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Saldanha, and A. Taubin.
Partial scan delay fault testing of asynchronous circuits.
In International Workshop on Logic Synthesis, May 1997.

82

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev.
Technology mapping for speed-independent circuits: decomposition and resynthesis.
In International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 240-253, April 1997.

83

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev.
Technology mapping for speed-independent circuits: decomposition and resynthesis.
In International Symposium on Advanced Research in Asynchronous Circuits and Systems, Groeningen, NL, March 1997.

84

L. Lavagno, J. Cortadella, and A. Sangiovanni-Vincentelli.
Embedded code optimization via common control structure detection.
In Proceedings of the International Workshop on Hardware-Software Codesign, March 1997.

85

R.S. Mitra, B. Bhattacharya, and L. Lavagno.
Asynchronous implementation of synchronous esterel specifications.
In Proceedings of the Tenth International Conference on VLSI Design, January 1997.

86

C. Passerone, L. Lavagno, M. Chiodo, and A. Sangiovanni-Vincentelli.
Fast hardware/software co-simulation for virtual prototyping and trade-off analysis.
In Proceedings of the Design Automation Conference, June 1997.

87

C. Passerone, L. Lavagno, C. Sansoè, M. Chiodo, and A. Sangiovanni-Vincentelli.
Trade-off evaluation in embedded system design via co-simulation.
In Proceedings of the Asian and South Pacific Design Automation Conference, January 1997.

88

A. Semenov, A. Yakovlev, E. Pastor, M. Pena, J. Cortadella, and L. Lavagno.
Partial order based approach to synthesis of speed-independent circuits.
In International Symposium on Advanced Research in Asynchronous Circuits and Systems, Groeningen, NL, March 1997.

89

R. von Hanxleden, L. Lavagno, and A. Sangiovanni-Vincentelli.
Co-Design of a Fault-Tolerant Communication Protocol - A Case Study.
Technical Report Memorandum No. UCB/ERL M97/13, U.C. Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, February 1997.

90

F. Balarin, L. Lavagno, and P. Murthy.
Scheduling for embedded real-time systems.
IEEE Design and Test of Computers, 15(1):71-82, January 1998.

91

G. Borriello, L. Lavagno, and R. Ortega.
Interface synthesis: a vertical slice from digital logic to software components.
In Proceedings of the International Conference on Computer-Aided Design, November 1998.

92

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev.
Automatic handshake expansion and reshuffling using concurrency reduction.
In International Workshop on Hardware Design and Petri Nets (part of International Conference on Application and Theory of Petri Nets), pages 86-110, June 1998.

93

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev.
Lazy transition systems: application to timing optimization of asynchronous circuits.
In Proceedings of the International Conference on Computer-Aided Design, November 1998.

94

J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev.
Deriving petri nets from finite transition systems.
IEEE Transactions on Computers, 47(8):859-882, August 1998.

95

E. Filippi, L. Lavagno, L. Licciardi, A. Montanaro, M. Paolini, R. Passerone, A. Sangiovanni-Vincentelli, and M. Sgroi.
Intellectual property re-use in embedded system co-design: an industrial case study.
In Proceedings of the International Symposium on System Synthesis, pages 37-42, December 1998.

96

Y.P. Hong, P. Beerel, L. Lavagno, and E. Sentovich.
Don't care-based BDD minimization for embedded software.
In Proceedings of the Design Automation Conference, June 1998.

97

A. Jurecska, A. Damiano, T. Cuatto, C. Passerone, L. Lavagno, C. Sansoe, and A. Sangiovanni-Vincentelli.
A case study in embedded system design: An engine control unit.
In Proceedings of the Design Automation Conference, June 1998.

98

M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Saldanha, and A. Taubin.
Partial scan delay fault testing of asynchronous circuits.
IEEE Transactions on Computer-Aided Design, 17(11), November 1998.

99

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Taubin.
The use of petri nets for the design and verification of asynchronous circuits and systems.
Journal of Circuits, Systems, and Computers, 8(1), February 1998.

100

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, A. Taubin, and A. Yakovlev.
Identifying state coding conflicts in asynchronous system specifications using petri net unfoldings.
In IEEE International Conference on Application of Concurrency to System Design, March 1998.

101

M. Lajolo, A. Raghunathan, S. Dey, L. Lavagno, and A. Sangiovanni-Vincentelli.
A case study on modeling shared memory access effects during performance analysis of HW/SW systems.
In Proceedings of the International Workshop on Hardware-Software Codesign, March 1998.

102

L. Lavagno and A. Sangiovanni-Vincentelli.
System-level design models and implementation techniques.
In IEEE International Conference on Application of Concurrency to System Design, March 1998.

103

L. Lavagno, A. Sangiovanni-Vincentelli, and E. Sentovich.
Models of computation for embedded system design.
In A. Jerraya and J. Mermet, editors, Nato Advanced Study Institute on System-Level Synthesis. Kluwer Academic Publisher, 1998.

104

R. Ortega, L. Lavagno, and G. Borriello.
Models and methods for HW/SW intellectual property interfacing.
In A. Jerraya and J. Mermet, editors, Nato Advanced Study Institute on System-Level Synthesis. Kluwer Academic Publisher, 1998.

105

C. Passerone, L. Lavagno, C. Sansoe', J. Martin, R. Passerone, R. McGeer, and A. Sangiovanni-Vincentelli.
Modeling reactive systems in java.
ACM Transactions on Design Automation of Electronic Systems, 3(4), October 1998.

106

F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. Sentovich, and K. Suzuki.
Synthesis of software programs for embedded control applications.
IEEE Transactions on Computer-Aided Design, June 1999.

107

Ivan Blunno and Luciano Lavagno.
Towards a language-based design flow for asynchronous circuits.
In Proceedings of the International Workshop on Logic Synthesis, June 1999.

108

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev.
Decomposition and technology mapping of speed-independent circuits using boolean relations.
IEEE Transactions on Computer-Aided Design, 18(9):834-849, September 1999.

109

H. Hsieh, A. Sangiovanni-Vincentelli, F. Balarin, and L. Lavagno.
Synchronous equivalence for embedded systems: a tool for design exploration.
In Proceedings of the International Conference on Computer-Aided Design, November 1999.

110

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev.
Automatic synthesis and optimization of partially specified asynchronous systems.
In Proceedings of the Design Automation Conference, June 1999.

111

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev.
Logic decomposition of speed-independent circuits.
Proceedings of the IEEE, 87(2), February 1999.

112

M. Lajolo, L. Lavagno, and A. Sangiovanni-Vincentelli.
Fast instruction cache simulation strategies in a hardware/software co-design environment.
In Proceedings of the Asian and South Pacific Design Automation Conference, January 1999.

113

M. Lajolo, L. Lavagno, and A. Sangiovanni-Vincentelli.
Fast instruction cache simulation for hardware/software co-design.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E82-A(11):2475-2484, November 1999.

114

M. Lajolo, A. Raghunathan, S. Dey, L. Lavagno, and A. Sangiovanni-Vincentelli.
Efficient power estimation techniques for hardware/software systems.
In Proceedings of International Volta '99 Conference, March 1999.

115

L. Lavagno and E. Sentovich.
ECL: A specification environment for system-level design.
In Proceedings of Design Automation Conference. DAC '99. New Orleans, June 1999.

116

Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, and Alexander Yakovlev.
What is the cost of delay insensitivity?
In Proceedings of the International Conference on Computer-Aided Design, pages 316-323, November 1999.

117

Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, and Alexander Yakovlev.
Bridging modularity and optimality: delay-insensitive interfacing in asynchronous circuits synthesis.
In IEEE International Conference on Systems, Man, and Cybernetics, October 1999.

118

A. Sangiovanni-Vincentelli, M. Re, L. Lavagno, and G. Cardarilli.
Analysis of the quantization noise effects on the SQNR behaviour in analog to digital conversion.
In Proceedings of the IEEE International Symposium on Circuits and Systems VLSI (ISCAS), June 1999.

119

M. Sgroi, L. Lavagno, Y. Watanabe, and A. Sangiovanni-Vincentelli.
Synthesis of embedded software using free-choice petri nets.
In Proceedings of Design Automation Conference. DAC '99. New Orleans, June 1999.

120

M. Sgroi, L. Lavagno, Y. Watanabe, and A. Sangiovanni-Vincentelli.
Quasi-static scheduling of embedded software using equal conflict nets.
In Proceedings of 20th International Conference on Application and Theory of Petri Nets. ICATPN '99, June 1999.

121

B. Tabbara, E. Filippi, L. Lavagno, M. Sgroi, and A. Sangiovanni-Vincentelli.
Fast hardware/software co-simulation using VHDL models.
In Proceedings of the Conference on Design Automation and Test in Europe, March 1999.

122

A. Taubin, A. Kondratyev, J. Cortadella, and L.Lavagno.
Behavioral transformations to increase the noise immunity of asynchronous specifications.
In International Symposium on Advanced Research in Asynchronous Circuits and Systems, Barcelona, Spain, April 1999.

123

J.R. Bammi, E. Harcourt, W. Kruitzer, L. Lavagno, and M.T. Lazarescu.
Software performance estimation strategies in a system-level design tool.
In Proceedings International Workshop on Hardware/Software Codesign, May 2000.

124

I. Blunno and L. Lavagno.
Automated synthesis of micro-pipelines from behavioral Verilog HDL.
In Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 2000.

125

J. Cortadella, A. Kondratyev, L. Lavagno, L. Massot, C. Passerone, and Y. Watanabe.
Task generation and compile-time scheduling for mixed data-control embedded software.
In Proceedings IEEE Design Automation Conference, June 2000.

126

H. Hsieh, F. Balarin, L. Lavagno, and A. Sangiovanni-Vincentelli.
Efficient methods for embedded system design space exploration.
In Proceedings IEEE Design Automation Conference, June 2000.

127

C. Kim, L. Lavagno, and A. Sangiovanni-Vincentelli.
Free MDD-based software optimization techniques for embedded systems.
In Proceedings IEEE Design Automation and Test in Europe Conference, March 2000.

128

M. Lajolo, L. Lavagno, and M. Rebaudengo.
Automatic test bench generation for simulation-based validation.
In Proceedings International Workshop on Hardware/Software Codesign, May 2000.

129

M. Lajolo, A. Ragunathan, S. Dey, and L. Lavagno.
Efficient power co-estimation techniques for system-on-chip design.
In Proceedings IEEE Design Automation and Test in Europe Conference, March 2000.

130

M. Lajolo, M. Rebaudengo, M. Sonza-Reorda, M. Violante, and L. Lavagno.
Evaluating system dependability in a co-design framework.
In Proceedings IEEE Design Automation and Test in Europe Conference, March 2000.

131

M. Lajolo, M. Rebaudengo, M. Sonza-Reorda, M. Violante, and L. Lavagno.
System-level test bench generation in a co-design framework.
In Proceedings IEEE European Test Workshop, May 2000.

132

M. Lajolo, M. Rebaudengo, M. Sonza-Reorda, M. Violante, and L. Lavagno.
Behavioral-level test vector generation for system-on-chip designs.
In Proceedings IEEE International High-Level Design Validation and Test Workshop, November 2000.

133

L. Lavagno, B. Pino, L.M. Reyneri, and A. Serra.
A simulink(c)-based approach to system level design and architecture selection.
In Proceedings of the 26th Euromicro Conference, September 2000.

134

L. Lavagno, T. Villa, and A. Sangiovanni-Vincentelli.
Advances in encoding for logic synthesis.
In G. Zobrist, editor, VLSI Design Environments. Gordon and Breach Science Publishers, 2000.
(invited chapter).

135

M.T. Lazarescu, J.R. Bammi, E. Harcourt, and L. Lavagno.
Compilation-based software performance estimation for system level design.
In Proceedings IEEE International High-Level Design Validation and Test Workshop, November 2000.

136

S. Quer, G. Cabodi, P. Camurati, L. Lavagno, and E. Sentovich.
Verification of similar FSMs by mixing incremental re-encoding, reachability analysis, and combinational checks.
Formal Methods in System Design, 17(2):107-134, 2000.

137

L.M. Reyneri, M. Chiaberge, L. Lavagno, and B. Pino.
Simulink-based HW/SW codesign of embedded neuro-fuzzy systems.
International Journal of Neural Systems, 10(3):211-226, June 2000.

138

A. Sangiovanni-Vincentelli, M. Sgroi, and L. Lavagno.
Formal models for communication-based design.
In International Conference on Concurrency Theory, August 2000.

139

M. Sgroi, L. Lavagno, and A. Sangiovanni-Vincentelli.
Formal models for communication-based design.
IEEE Design and Test of Computers, 17(2):14-27, April 2000.

140

M. Antoniotti, A. Ferrari, L. Lavagno, E. Sentovich, and A. Sangiovanni-Vincentelli.
Embedded system design specification: Merging reactive control and data computation.
In Proceedings of IEEE Conference on Decision and Control, December 2001.

141

F. Balarin, J. Burch, L. Lavagno, Y. Watanabe, R. Passerone, and A. Sangiovanni-Vincentelli.
Constraints specification at higher levels of abstraction.
In Proceedings IEEE International High-Level Design Validation and Test Workshop, November 2001.

142

A. Chatelain, Y. Mathys, G. Placido, A. La Rosa, and L. Lavagno.
High-level architectural co-simulation using esterel and c.
In Proceedings International Workshop on Hardware/Software Codesign, April 2001.

143

L. Lavagno, A. La Rosa, and C. Passerone.
A software development tool chain for a reconfigurable processor.
In Proceedings of the international conference on compilers architecture and synthesis for embedded systems (CASES), November 2001.

144

R. Marculescu, A. Nandi, L. Lavagno, and A. Sangiovanni-Vincentelli.
System-level power/performance analysis of portable multimedia systems communicating over wireless channels.
In Proceedings of the International Conference on Computer-Aided Design, November 2001.

145

G. Martin, L. Lavagno, and J. Louis-Guerin.
Embedded UML: a merger of real-time UML and co-design.
In Proceedings International Workshop on Hardware/Software Codesign, April 2001.

146

C. Passerone, Y. Watanabe, and L. Lavagno.
Generation of minimal size code for schedule graphs.
In Proceedings IEEE Design Automation and Test in Europe Conference, March 2001.

147

L. Reyneri, F. Cucinotta, A. Serra, and L. Lavagno.
A hardware/software co-design flow and IP library based on Simulink.
In Proceedings IEEE Design Automation Conference, June 2001.

148

G. Arrigoni, L. Duchini, L. Lavagno, C. Passerone, and Y. Watanabe.
False path elimination in quasi-static scheduling.
In Proceedings of the Conference on Design Automation and Test in Europe, March 2002.

149

F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, and Y. Watanabe.
Modeling and designing heterogeneous systems.
In A. Yakovlev and J. Cortadella, editors, Advances in Concurrency and Hardware Design, Lecture Notes in Computer Science. Springer-Verlag, 2002.

150

F. Balarin, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, Y. Watanabe, and G. Yang.
Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model.
In Proceedings International Workshop on Hardware/Software Codesign, May 2002.

151

F. Balarin, L. Lavagno, C. Passerone, and Y. Watanabe.
Processes, interfaces and platforms. embedded software modeling in metropolis.
In Proceedings of the International Workshop on Embedded Software (EMSOFT), Lecture Notes in Computer Science. Springer-Verlag, October 2002.

152

I. Blunno and L. Lavagno.
Designing an asynchronous microcontroller using Pipefitter.
In Proceedings of the International Conference on Computer Design, September 2002.

153

G. Cabodi, M. Lazarescu, L. Lavagno, S. Nocco, C. Passerone, and S. Quer.
A symbolic approach for the combined solution of scheduling and allocation.
In Proceedings of the International Symposium on System Synthesis, October 2002.

154

R. Chen, M. Sgroi, G. Martin, L. Lavagno, A. Sangiovanni-Vincentelli, and J. Rabaey.
Embedded system design using UML and platforms.
In Proceedings of the International Workshop on Formal Design Languages (FDL), September 2002.

155

J. Cortadella, A. Kondratyev, L. Lavagno, C. Passerone, and Y. Watanabe.
Quasi-static scheduling of independent tasks for reactive systems.
In Proceedings of the International Conference on Application and Theory of Petri Nets. ICATPN, June 2002.

156

Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, , and Alexandre Yakovlev.
Logic synthesis for asynchronous controllers and interfaces.
Springer-Verlag, 2002.

157

L. Lavagno and S. Nowick.
Asynchronous control circuits.
In S. Hassoun and T. Sasao, editors, Logic synthesis and verification. Kluwer Academic Publishers, 2002.

158

Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Takashi Nanya, and Alexander Yakovlev.
Design of asynchronous controllers with delay insensitive interface.
Transactions of the IEICE, March 2002.

159

F. Balarin, Y. Watanabe, H. Hsieh, L. Lavagno, C. Passerone, and A. Sangiovanni-Vincentelli.
Metropolis: An integrated electronic system design environment.
IEEE Computer, 36(2):45-52, April 2003.

160

F. Campi, R. Canegallo, A. Cappelli, R. Guerrieri, A. La Rosa, L. Lavagno, A. Lodi, C. Passerone, and M. Toma.
A reconfigurable processor architecture and software development environment for embedded systems.
In Proceedings of the International Parallel and Distributed Processing Symposium, April 2003.

161

J. Cortadella, A. Kondratyev, L. Lavagno, and Y. Watanabe.
Quasi-static scheduling for concurrent architectures.
In Proceedings of International Conference on Application of Concurrency to System Design, June 2003.

162

L. Lavagno, A. La Rosa, and C. Passerone.
Hardware/software design space exploration for a reconfigurable processor.
In Proceedings of the Conference on Design Automation and Test in Europe, March 2003.

163

C.P. Sotiriou and L. Lavagno.
Desynchronization: Asynchronous circuits from synchronous specifications.
In Proceedings of the IEEE International SOC Conference, September 2003.

164

L. Vanzago, B. Bhattacharya, J. Cambonie, and L. Lavagno.
Design space exploration for a wireless protocol on a reconfigurable platform.
In Proceedings of the Conference on Design Automation and Test in Europe, March 2003.